As a technology related to the drive circuit of the existing liquid crystal display device, the present field has developed a GOA (Gate-driver on Array) technology, that is, the gate drive circuit is directly integrated on the display array substrate of the liquid crystal display device through photolithographic process. The GOA circuit generally comprises a plurality of cascaded shift register units, each shift register unit connects with a shift register unit in the adjacent row respectively, each shift register unit corresponds to a row of gate line, each shift register unit may provide the output signal to a next shift register unit while outputting the gate drive signal, so as to ensure that the next shift register unit can output the gate drive signal within the next clock period.
However, in the shift register unit adopted in most GOA structures at present, the control node of the output transistor may be always in a floating state under a certain clock signal, the potential at this node may be influenced by electric leakage of surrounding transistors, which may result in change of the gate control potential of the output transistor, thereby influencing stable output of the shift register.
FIG. 1 shows a schematic view of the circuit structure of an 8T1C shift register unit in the prior art. FIG. 2 shows signal timing waveforms of the 8T1C shift register unit as shown in FIG. 1. As shown, the shift register unit comprises two clock inputs CLK1 and CLK2, the two clock signals inputted by which have the same period, but being opposite in phase. In addition, the shift register unit further comprises an input end STV and an output end OUT, and the output end outputs shifted input signals. In actual use, the gate drive circuit of the liquid crystal display device comprises a plurality of cascaded shift registers, the input end of the first shift register receiving frame scan start pulse signal STV, the input end of each subsequent shift register receiving the output signal of the previous shift register. In this way, each shift register outputs a respective STV signal experiencing different times of shifting, i.e., Out_put1, Out_put2 . . . . Wherein the STV signal indicates start of a frame, after it is inputted into a plurality of cascaded shift registers, each of the plurality of shift registers outputs a respective STV signal experiencing different times of shifting, which can act as the gate row drive signal for the corresponding row in the display array substrate of the liquid crystal display device, for driving display of the corresponding row of pixels in the display array substrate of the liquid crystal display device.
The defect as stated above exists exactly in the shift register unit as shown in FIG. 1, that is, under a certain clock signal, the control node of the output transistor may be always in a floating state, the potential at this node may be influenced by electric leakage of surrounding transistors, which may result in change of the gate control potential of the output transistor, thereby influencing stable output of the shift register.
Specifically, in the circuit structure of the shift register unit as shown in FIG. 1, the transistor M19 is an output transistor, whose control node is the node A at its gate. The node A will be always in a floating state under the second, third, fourth clock signals of CLK2, thereby an unstable signal occurs, as shown in the waveform in line 4 of FIG. 2. The reason for this is that prior to the second, third, fourth clock signals of the second clock signal CLK2, the node C keeps a relatively high signal, while the node A keeps a relatively low signal. When a low level signal occurs in the second, third, fourth clock signals of CLK2, this low level signal opens the transistor M20, thereby enabling the node A and the node C to be connected by a conductive path. Moreover, at this point, neither of these two nodes are supplied with voltage by an external direct signal source, hence, unstable signals may occur at both node A and node C, the node A that should keep a low potential will be pulled higher, thus resulting in worse output of the output transistor M19 and influencing the output signal Out of the shift register.
Therefore, there is a need in the art to provide an improved shift register unit, so as to overcome the above defects in the shift register unit of the prior art.